Traditionally integrated circuit modules are mounted on a resin-based copper clad circuit board providing for the interconnection of signals between circuit modules or chips. Such interconnects typically are made by photolithographic and etching techniques that leave a circuit pattern representing the routing of a signal from one circuit node to one or more other circuit nodes. Such printed circuit or wiring board (PCB or PWB) techniques are compatible with the production of a more recent advent of multi-chip modules (MCMs). Typically, MCMs mount ICs on thin-film substrates mounted, in turn, on a rigid carrier. For example, signal, power and ground traces are laid down using conventional routing PCB or PWB techniques on 6-7 layer substrates, e.g. by photolithographic masking, etching and/or sputtering, to provide the needed increased signal routing densities. An overview of conventional MCM production techniques is presented in AN OVERVIEW OF MULTICHIP MODULES, by Pradeep Lall, et al., which was published in September 1993 in Solid State Technology magazine, with which familiarity is assumed.
There are limits to the number of signals that may be routed using such techniques, since there are signal cross-talk, current density and heat build-up concerns with increasingly tiny signal conductor widths (in the micron range) and with increasing signal conductor routing densities or pitches (also in the micron range). Practically speaking, no more than a few hundred interconnections may be provided with conventional techniques in boards of modest size and packing density.
U.S. Pat. No. 4,498,122 entitled HIGH-SPEED, HIGH PIN-OUT LSI CHIP PACKAGE, which issued Feb. 5, 1985, teaches the use of vertical metal pillars, or vias, to route signals between layers of a multi-layer PCB having power and ground planes, and also teaches the use of dielectric material to separate adjacent layers, each of which routes signals between vias unidirectionally and otherwise by conventional photolithographic tiny signal conductor routing techniques. That patent does not suggest the dedication of a layer to each interconnect signal. Nor does that patent suggest substrate programmability nor the rendering of each signal layer substantially coextensive with the substrate.
U.S. Pat. No. 4,888,665 entitled CUSTOMIZABLE CIRCUITRY, which issued Dec. 19, 1989, teaches a programmable interconnect circuit that uses orthogonally extending multi-wire layers adjacent ones of which can be fused and anti-fused as necessary to program interconnect nodes. That patent does not teach through vias nor dedicated per-signal interconnect extensive planar multi-layers in a programmable MCM or like structure.
U.S. Pat. No. 4,899,439 entitled METHOD OF FABRICATING A HIGH DENSITY ELECTRICAL INTERCONNECT, which issued Feb. 13, 1990, teaches orthogonal X and Y conductor strips and corresponding X and Y metal pillars fabricated to electrically connect therewith, with an X and a Y crossing being rendered conductive by providing a metal conducting pillar segment therebetween. A ground plane provided on the substrate avoids electrical contact with the vertical pillars by forming insulating buffer regions therearound. Conventional deposition techniques are used to provide SiO.sub.2 insulation and Cu conductors, with the three-dimensional interconnect substrate being filled with an air or other desired dielectric. That patent does not teach dedicated per-signal interconnect extensive planar multi-layers in a programmable MCM or like structure.
U.S. Pat. No. 5,264,664 entitled PROGRAMMABLE CHIP TO CIRCUIT BOARD CONNECTOR, which issued Nov. 23, 1993, teaches a programmable chip-to-PCB interconnections using a matrix of connection pads and associated regularly arrayed vias, the programming being performed by masked metal deposition to bridge a selected via and a selected pad. Selectively deposited passivation layers of polyamide protect against inadvertent bridging of via/pad gaps during chip lead soldering. FIG. 4 shows plural vertical vias extending to different depths to provide an interconnect with one of plural mesh planes, which are voltage or ground planes, not signal planes. That patent does not teach dedicated per-interconnect signal, co-extensive planar multi-layers in a MCM or like structure.
U.S. Pat. No. 5,373,109 entitled ELECTRICAL CABLE HAVING FLAT, FLEXIBLE, MULTIPLE CONDUCTOR SECTIONS, which issued Dec. 13, 1994, teaches an electrical wiring cable having flat, flexible, multiple-signal-conductor layers stacked vertically atop one another and insulated by dielectric layers therebetween and having also one or more ground planes, each inner layer for routing a signal from one edge-stepped, conductor-exposing end to another. That patent does not suggest vertical vias for selective interconnecting of dedicated signal layers and does not suggest MCM substrates or other IC-mounting structures.
Laser ablation and etching represent recent developments applicable to thin film substrates for the removal and deposition of material from a solid surface. Briefly, laser ablation involves excitation of a solid's molecules and larger particles by irradiation by high-power, short-pulse lasering. Laser etching differs therefrom in that it involves 1) chemical reactions, e.g. chemisorption and bulk diffusion, at an interface between a solid surface and a background gas and 2) irradiation to produce desorption of the chemically reacted layer. Laser ablation and etching are believed to lend themselves to highly-controlled, selective removal and deposition of materials in the microcircuit fabrication field where fine patterning is required, and at etch rates similar to those obtained in plasma reactors. Such laser techniques are described in LASER ABLATION AND LASER ETCHING, by Boulmer, et al., which was published in 1992 by Elsevier Science Publishers, B.V. See also COMPARISON OF THE ABLATION OF DIELECTRICS AND METALS AT HIGH AND LOW LASER POWERS, by Dreyfus, which was published in 1992 by Elsevier Science Publishers, B.V. Familiarity with these publications is assumed.